1. Field of the Invention
The present invention relates to an MOSFET, and more particularly, to a structure and fabricating method of an MOSFET.
2. Discussion of the Related Art
There has been a general trend for the past ten years towards micronization and high device density packing of MOS devices. The number of devices packed on a single chip has doubled every year. To meet this trend, the size and parasitic capacitance of the device needed reduction for obtaining a high speed device which is packed under ultra large scale integration (ULSI).
However, a conventional bulk CMOS structure has the following problems in reducing the size and parasitic capacitance of the device. First, it is impossible to reduce the width of isolation between a P-channel and N-channel without loss of the latch-up immunity. Second, an alpha particle that induces soft error problems places limitations on the amount of minimum singular charge, which in turn places limitations on the size of the device and voltage supply. Third, the parasitic capacitance between the source/drain and the substrate limits reduction of the device size.
In the meantime, an SOI (Silicon-On-Insulator) has been very effective for reducing the size and parasitic capacitance of the device, because it can provide ideal isolation and low parasitic resistance. Accordingly, the SOI structure is partly combined with the CMOS structure for providing effects identical to the SOI structure.
However, although the CMOS structure to which the SOI has been partly combined has been very effective for the next generation ULSI devices, it has many problems. Such problems include a limitation on the amount of reduction of the channel length and longer manufacturing time.
A conventional MOSFET structure and a method tor fabricating the conventional MOSFET structure will be explained hereinafter with reference to the attached drawings.
FIG. 1 illustrates a section of a conventional MOSFET structure. As shown in FIG. 1, the conventional MOSFET includes a gate electrode 7 formed on a substrate 1, a source region and a drain region 8 formed in the substrate 1 at both sides of the gate electrode 7, an oxide film 3 having vertical sidewalls formed to surround the source region and drain region 8, and a well region 2 formed below the oxide film 3 containing the source region and the drain region 8.
FIGS. 2a to 2f illustrate a conventional method for fabricating an MOSFET. As shown in FIG. 2a, a field region and an active region are defined on a semiconductor substrates 1. The active region is subjected to boron and phosphor ion injection, for the first time, for forming an N-well and a P-well to form well regions 2.
As shown in FIG. 2b, the substrate 1 is thermally oxidized to form an oxide film 3 on an entire surface of the substrate 1. As shown in FIG. 2c, the oxide film 3 is selectively etched to form contact holes 4 which expose the well regions 2.
Each of the contact holes 4 is etched so that the contact hole 4 has a recessed region 5 at an upper part of the contact hole 4. The recessed region 5 determines the device size and seed regions as well as the depth of the source and drain.
In order to adjust an impurity concentration in a depth of an epitaxial silicon layer, boron (B) and phosphorous (P) ions are injected, for the second time, into the substrate 1 having the contact holes 4, formed thereon.
As shown in FIG. 2d, an undoped epitaxial silicon layer 6 is selectively grown starting from the contact holes 4, each having the recessed region 5. As shown in FIG. 2e, the epitaxial silicon layer is polished selectively to expose the oxide film 3.
In order to fix transistor performances, boron (B) and phosphorous (P) ions are injected, for the third time, into the epitaxial silicon layers 6 remained between the oxide films 3.
As shown in FIG. 2f, a gate electrode 7 is formed on each of the epitaxial silicon layers 6 which are surrounded by the oxide films 3, and ions are injected into the substrate 1 on both sides of the gate electrodes 7 to form the source and drain regions 8.
However, the aforementioned conventional MOSFET structure and the fabricating method have the following problems. First, due to the punch through effect between the source and drain, decreasing of the channel length is limited. Second, the epitaxial silicon layer growth takes a long time. Third, it is hard to control the distance between the N-well and the P-well due to the lengthy time required for growing the epitaxial layer.